1. Field of the Invention
The present invention relates to random access semiconductor memory devices, and more particularly to the technique of employing a memory cell that is formed including a transistor with a storage node.
2. Description of the Background Art
Although the DRAM (Dynamic Random Access Memory) formed of stacked type or trench type memory capacitors and transistors for switching assumes a dominant position in the field of semiconductor memory devices of high density, it is now reaching the scaling limitation due to the difficulty in microminiaturization of the memory capacitor. Under such circumstances, there is proposed a memory cell that employs the transistor per se as the capacitor element as an alternative to the configuration that includes a memory capacitor such as the DRAM.
Among such new type of memory cells, there is known a promising twin transistor RAM (TTRAM: Twin Transistor Random Access Memory). For example, T. Gyohten et al. disclose, in “A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI”, THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, IEICE Technical Report, vol. 105, No. 349, pp. 107-112, Oct. 20, 2005, a capacitorless twin-transistor RAM having charge accumulated at a floating body region of an SOI (Silicon On Insulate) transistor to store data.
Further, Japanese Patent Laying-Open No. 2005-302077 discloses a semiconductor memory device including a memory cell (FBC: Floating Body Cell) for storing data by accumulating or releasing charge with respect to a floating body region that is electrically in a floating state.
In such a memory cell that employs a transistor per se as a capacitor element, the read current flows through the neighborhood of a storage node that accumulates charge, and current leakage occurs through the junction between the storage node and an adjacent source region or drain region. Accordingly, there was a problem that the retaining capability of stored data is degraded in the aspect of dynamic noise from a control line or the like electrically connected to the memory cell.